1. Field of the Invention
The invention relates to computer busing systems, and more particularly to a method of and apparatus for individually disabling specific slots independent of the address asserted on the system bus.
2. Description of the Related Art
The microcomputer industry has experienced tremendous growth over the last twenty years. From the days of its infancy when only a few interested "hackers" could fathom its quirks and nuances, the microcomputer has now evolved into a powerful business and personal tool found on virtually every office desk and in virtually every home.
The microcomputer's road to success has not been without its problems, however. While advances occur at an astounding pace, those advances must accommodate the standards found in the then existing base of microcomputer systems. This is known as upwards compatibility. To maintain such compatibility, the industry has seen one microcomputer standard laid on top of another, with a resulting hodgepodge of standards-within-standards that designers must maintain to allow existing users to upgrade their equipment. These multiple standards gradually shed their oldest layers, replacing them with new layers reflecting the state-of-the-art. In this way, only the very oldest microcomputer systems become obsolete.
One early idea to enhance microcomputer systems was the addition of hardware enhancing cards. These cards were generally plugged into a system bus to provide added functionality, such as telecommunications, disk storage, and improved video. These cards obviously had to conform to some standard. With the introduction of the IBM PC by International Business Machines Corp., and the later introduction of the PC/AT by IBM, the AT system bus soon became a de facto standard known as the Industry Standard Architecture bus, or the ISA bus. The AT bus accommodated both the 8-bit cards of the PC and newer 16-bit cards developed for the AT. Third-party manufacturers could economically design standard cards compatible with the wide variety of IBM PC and AT compatible microcomputer systems.
Further advances in microprocessor technology, however, pushed the ISA bus to its limits. For this reason, another "layer" was added to the ISA bus standard. This added layer became known as the Extended Industry Standard Architecture bus, or the EISA bus. Cards designed for the EISA bus had more pins, providing a wider data path for information to flow through the microcomputer system bus, analogous to adding lanes to a highway. The EISA bus also added more address lines to the standard, permitting more memory locations to be individually specified, much as would adding more digits to a phone number or a zip code.
Along with its improved information pathways, however, the EISA bus brought certain problems. The EISA bus standard had to accommodate existing ISA cards to provide upwards compatibility. The ISA bus, however, not only had fewer data and address lines, but also had only enough control lines to handle the smaller size of those data and address lines. The broader data and addressing width of the EISA bus demanded more control signals. This resulted in a two-layer standard.
While the ISA standard provided 16 bits of I/O addressing, in developing cards for PC-compatible computers, vendors often only used or decoded the lower 10 bits. Thus, to be fully compatible with the available cards, the I/O address space of the ISA bus effectively was only from 0 to 03FFh. Thus, a large portion of the I/O space was unusable.
Another limitation of the ISA bus involved its method of handling I/O and memory addressing. An address enable signal (AEN) was driven low by an ISA bus master to indicate to all of the cards that the currently asserted address was an I/O address or a memory address rather than a direct memory access (DMA) operation. But because AEN was asserted low to all cards, each card had to be physically configured to respond to a different range of I/O and memory addresses to avoid conflicts. This address differentiation was usually accomplished when installing the boards by setting microswitches on dual in-line packages (DIP) or by connecting jumpers on each board. Improperly setting these switches could result in conflicts on a read or write to a particular I/O and memory address and could even result in physical hardware damage.
The EISA bus standard has resolved this problem to some extent. The EISA bus definition provides for a conflict-free I/O address space for each slot. This is fully described in U.S. Pat. No. 4,999,805, and the EISA Specification, Version 3.1, which is Appendix 1 of U.S. Pat. No. 4,101,492, both of which are hereby incorporated by reference. The expansion board manufacturers include a configuration file with each EISA expansion board, and optionally, with switch programmable ISA products. A configuration utility program provided by the system manufacturer uses the information contained in the configuration files to determine a conflict-free configuration of the system resources. The configuration utility stores the configuration and initialization information into non-volatile memory and saves a backup copy on diskette. Details of this configuration process are provided in Ser. No. 07/293,315, entitled "Method and Apparatus for Configuration of Computer System and Circuit Boards," allowed on May 10, 1993, which is hereby incorporated by reference. The system ROM power up routines use the initialization information to initialize the system during power up, and device drivers use the configuration information to configure the expansion boards during operation.
Expansion boards install into EISA and ISA bus connectors. Each bus connector is referred to as a slot. The bus connectors are numbered sequentially from 1 to "Z" (with 14 as the maximum "Z"). For example, an EISA system with 7 bus connectors has slots numbered from slot 1 to slot 7. Slots 0 and 15 are reserved for the system board. The system board mounts the slot connectors and can also include individual EISA or ISA devices of its own.
An EISA bus controller on the system board has I/O address decoding hardware that provides each EISA slot with a unique, 1,024 byte, slot specific I/O address space. The slot specific information is decoded as follows. EISA systems reserve I/O spaces at 0Z00h-0Z0FFh, 0Z400h-0Z4FFh, 0Z800h-0Z8FFh, and 0Zc00h-0ZcFFh for slot specific I/O slaves on ISA and EISA expansion boards. These address ranges do not conflict with ISA board I/O addresses because they alias ISA system board I/O address space. EISA system boards must fully decode system board I/O accesses to ensure they do not alias with slot specific I/O slaves. The system board uses the slot specific I/O range where "Z" is 0 or 15 for all system I/O devices.
The system board disables the slot specific I/O ranges to the non-selected slot by asserting a slot specific bus signal AENx high (where "x" is the slot number) if the address "Z" does not match the slot number and the least significant 12 address bits address a slot specific range (0Z00h-0Z0FFh, 0Z400h-0Z4FFh, 0Z800h-0Z8FFh, 0Zc00h-0ZcFFh). Expansion boards that take advantage of the slot specific I/O ranges must, at a minimum, decode the LA[8] and LA[9] address bits to "0" with AENx negated (low) to assure they do not alias with ISA expansion board I/O. This is all more fully detailed in U.S. Pat. No. 4,999,805, and in the EISA Specification Version 3.1, both of which are above incorporated by reference.
A problem with both the ISA and EISA specifications is that there is no way to prevent conflicts between ISA boards residing in the same non-slot specific I/O address space or residing in the same memory space. When an ISA expansion board I/O or memory address is accessed and that address is occupied by two ISA boards, both will attempt to drive the data bus in response to that address. This is because on accesses to ISA I/O addresses or memory addresses, all of the AENx bus signals are asserted low. This, of course, can lead to both unpredictable and undesirable results. Thus, it would be desirable to determine the possibility of such conflicts before they occur.
Further, it is difficult to determine in which slot a card using ISA I/O addressing or containing memory is located. EISA cards are readily located and their identity determined by reading defined slot specific registers. But no such registers exist for ISA cards. This, combined with all the AEN or AENx signals being asserted low on ISA slot space accesses, renders it effectively impossible to simply provide a given address and look for a response, as the responding unit could be located in any slot and all the responses would be identical. Thus, it is also desirable to be able to determine the location of the particular board for configuration purposes.